library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use work.alu_type.all;


entity TB_ALU is
end TB_ALU;

architecture TEST_ALU of TB_ALU is
component Arithmetic_Logic_Unit is
generic (	N : integer := 32;
		M : integer := 5);
port(	left			: in   std_logic_vector (N-1 downto 0);	-- left operand (A or NPC)
		right			: in   std_logic_vector (N-1 downto 0);	-- right operand (B or Imm)
		alu_opcode	: in   TYPE_OP;	-- operation to perform (activates the correct output)
		shamt		: in   std_logic_vector (M-1 downto 0);	-- shift amount
		output		: out std_logic_vector (N-1 downto 0);	-- ALU output
		status		: out std_logic								-- unused (should set the OF flag)
);
end component;

signal left		: std_logic_vector (31 downto 0);
signal right	: std_logic_vector (31 downto 0);
signal ALUopc	: TYPE_OP;
signal shamt	: std_logic_vector (4 downto 0);
signal output	: std_logic_vector (31 downto 0);
signal status	: std_logic;


begin


left <= std_logic_vector(to_unsigned(4,32)) after 0 ns;
right<= std_logic_vector(to_unsigned(12,32)) after 0 ns;
shamt <= "00000" after 0 ns;
aluopc <=BIT_AND after 0 ns, BIT_OR after 50 ns, BIT_XOR after 100 ns;

ALU: arithmetic_logic_unit port
map (	left			=> left,
		right			=> right,
		alu_opcode	=> ALUopc,
		shamt		=> shamt,
		output		=> output,
		status		=> status
);


end TEST_ALU;
